Chao WANG

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Chao WANG

Birthday:      Oct. 18 1981    
Nationality:   China    
Email:          swisschao@gmail.com   
Tel:              +41 762188688


EDUCATION

2007 - 2011 Neuchâtel, Switzerland
Ecole Polytechnique Fédérale de Lausanne(EPFL)  
Swiss Federal Institutes of Technology       
  • PhD of Microelectronics
Low power analog design, 
   CMOS photon sensor design, electronic products system design
Cadence, VHDL, FPGA, LabView, Matlab

2004–2007 Gardanne, France
Ecole Nationale Supérieur des Mines de St-Etienne
Centre Microélectronique de Provence - Georges Charpak
        
  • Master’s Degree of Microelectronics (ISMEA, a French engineer degree)
    • Option in Microelectronics Designing
  VHDL, System C, C/C++, Analogical and digital systems designing
  Architecture of Microprocessor , CAD Tools, Cadence Environment, Synopsys
  Embedded Systems, FPGA, Technologies and Processes of Semiconductor Fabrication
    • General Skills in Electronics and Informatics
Microcontrollers C51s and PICs, Labview, JAVA, VB, VC, Perl, Data Basis, UML, Compilation chain
Automatics, Digital Signal Processing, Radio Communication

2000-2004 Nanjing, China
Nanjing University of Science & Technology (NUST)
  • Bachelor’s Degree of Engineering
    • major in Environment and Equipments of Buildings.

EXPERIENCES

3/2007-9/2007 Geneva, Switzerland
Internship in STMicroelectronics
  • Develop a bit-true simulation chain for transmitter UWB
  • Test sub-modules (in SystemC), write programs for simulation bit-true.
  • Optimization for a sub module and write an interface (in Perl/tk ) for simplifying the development process.

3/2006-6/2006 Gardanne, France
Industrial Project for INTERSCIENCE
  • Designing a digital card for a new Spiral Automate of INTERSCIENCE
  • Analyzing different families of Microcontrollers and motor drivers (PIC, Allegro, Trinamic)
  • Designing an experimental card (Hardware & C programs) which can control 4 motors in different moving modes.

5/2005-9/2005 Rousset, France
Internship in STMicroelectronics
    • Studying the aging of the etching machine
    • Studying the structure of the etching machine and collect all the running dates of the machine for about 4 months.
    • Studying the dates (by Matlab) and write a report for the further research (statistical process control).

LANGUAGES

English:  advanced level (TOIEC 745)     
Chinese: mother language     
French:   advanced level